Communication between an external source and a microprocessor is typically controlled by both the external source and the microprocessor. One type of microprocessor system is an instruction pre-fetch microprocessor in which the microprocessor processes microinstructions in one or two cycles. The microinstructions are fetched from storage in a manner such that the next microinstruction is fetched during the execution of the current instruction.
In such pre-fetch microprocessor systems, interrupts from an external source typically have been masked or inhibited during certain instructions. Microprocessor instructions include arithmetic and logic instructions, input/output (I/O) instructions, storage read and write instructions and branch instructions. Due to the nature of a microprocessor pre-fetch system, previously developed systems have inhibited interrupts from being processed during storage read and write and branch instructions. Such systems have suffered from slow processing of these types of interrupts from the external I/O peripheral devices.
A need has thus arisen for an interrupt processing system for use with an instruction pre-fetch microprocessor system in which the capabilities of instruction pre-fetch are combined with efficient interrupt processing and response. A need has further arisen for an interrupt system in which arithmetic and logic unit status bits and page information is retained during an external interrupt until processing of the interrupt has been completed and wherein this saved data is restored to the processor. A need has further arisen for an instruction pre-fetch microprocessor interrupt system in which the use of less efficient software is eliminated to provide a system in which external interrupts are processed quickly.